The 67th Annual IEEE International Electron Devices Meeting is going on in San Francisco in these days (11-15 December 2021) and NaMLab is participating with two co-author contributions!
The first one is within the FVLLMONTI project. Interact with Cristell Maneux (IMS) during her talk: Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence. Discuss with Zlatan Stanojević (GTS) about the subband Boltzmann Transport (SBTE) methodology. Zlatan demonstrates how SBTE can be employed both as a path-finding tool and as a fundamental component in a DTCO flow.
The second one is within the 3eFerro project. Here you will see a 16 kbit 1T-1C FeRAM array fabricated at 130 nm node with TiN/HfO2:Si/TiN ferroelectric capacitors integrated in the Back-End of Line (BEOL). Zero bit failure is reported at the array level, with memory window fully opened down to 2.5 V, capacitor area down to 0.16 µm² and switching speed down to 4 ns. Promising endurance is reported at the array level up to 107 cycles. Last but not least, for the first time, solder reflow compatibility is demonstrated for HfO2-based FeRAM.