Classical RFETs employ a volatile electrical signal to dynamically program the functionality of the device, i.e. p- and n-conduction are steered only upon constant biasing of the program gates. We currently develop an option to store information within nanowire device for a longer time. Apart from classical data storage applications, this is of interest for hardware security, memory-in-logic and machine learning applications. For all those applications it is beneficial to store not only one, but multiple bits in a single cell. Currently, two approaches towards RFETs with embedded and non-volatile memory function are developed at NaMLab, a) the implementation of electron and hole trapping in silicon‑oxide/‑nitride based gate stacks and b) the integration of polarizable ferroelectric hafnia-zirconia based gate stacks.
As a first functional demonstrator a charge-trapping stack based on SiO2, SiXN1-x and a Ni metal gate (SONM stack in Fig. 1) was incorporated in omega shape around the nanowire channel of a dual gated RFET. The device was programmed in four distinct operation modes by volatile programming the polarity gate to differentiate between p- and n-type behaviour, and non-volatile programming the control gate to attain the set vs. the reset state that is represented by the threshold voltage of the device (Fig. 2). The four distinct operation modes can be changed reversibly when programming / erasing the two gates by application of respective voltage pulses in either polarity.
In order to reduce the operation voltage and increase the stability of the non-volatile programed function currently the integration of a ferroelectric gate material is developed. The main challenge here, as compared to charge trapping layers, is to yield a stable crystallization of the individual grains with respect to the three‑dimensional channel. Single gate Schottky FETs with Al-doped HfO2 as well as HfZrO2 ferroelectric materials were tested. Good results have been achieved on a trapezoidal nanowire etched from an SOI substrate (Fig. 3) demonstrating effective junction tuning between programmed (high VTH and low ION) and erased (low VTH and high ION) state. Our current work focuses on optimizing etching processes of HZO for dual gate implementation, the enlargement of the memory window and improvement of the endurance and retention properties.
Dr. Jens Trommer
cfaed – Center of Advancing Electronics Dresden (Germany), DCN – Dresden Center for Nanoanalysis (Germany)