Runtime-Reconfigurable Circuits

The multiple operation states of reconfigurable FETs open new opportunities for logic circuit design. Mainly, two features that were previously not accessible with conventional FETs are currently being studied. First, runtime-reconfigurable logic gates can be built, providing multiple functionalities as programmed on the fly by volatile select signals. Due to this reconfigurability, the overall value per building block is increased. One basic example is given by the compact cell, which can switch from NAND to NOR operation (Fig. 1). Distinctly, those cells always operate in a complementary manner, reaching a full swing output and exhibiting the same delay for both functions. The second feature is the integration of multiple gate electrodes along the nanowire channel, merging paths of series transistors within a single one, without increasing the internal resistance of the individual device. This feature can be exploited to build efficient XOR and Majority gates. Further, we recently showed the potential of such MIG/RFETs in dynamic logic gates as an elegant solution to reduce signal integrity risks such as the charge sharing effect.

Fig. 1: Mixed-mode simulations: runtime-reconfigurable operation of a NAND/NOR circuit cell with 6 transistors. The cell always delivers full swing output.

Based on our RFET device results, we have shown a comprehensive library of reconfigurable logic gates and combinational circuits. Promising examples are adders and arithmetic logic units (ALU) that are important elements of modern CPUs. An example of simple ALU exploiting the reconfigurable nature of our devices is shown in Fig. 2. We have demonstrated that RFETs based circuits can achieve a smaller overall area than equivalent circuits in CMOS, albeit the individual devices are larger. In addition, critical delay paths can be significantly improved, leading to a reduction of the overall structural delay on the system level by approximately 50%, under the constraint, that a similar individual device performance can be achieved.

Fig. 2:  Circuit schematic of a simple 1-bit ALU, exploiting runtime-reconfigurable logic gates.

To enable advanced and complex circuit design with RFETs the setup of a fully automated synthesis route was necessary, especially since RFET circuit design is fundamentally different than CMOS design. In cooperation with the excellence cluster CfAED at TU Dresden, automated logic and physical synthesis tools were developed making it possible to design deliberate logic circuits and to deliver the required layouts compatible with design rules of a 22 nm FDSOI technology (Fig. 3). With this route it is possible to assess and to perform benchmarks of the associated delay, power consumption and area use per function.

Fig. 3: Layout of a NAND/NOR cell compatible with 22 nm FDSOI design rules. The cell provides the same functionality as shown in Fig. 1.

Contact

Dr. Jens Tommer

Dr. Jens Trommer
Senior Scientist
Phone: +49 351 2124990-00
E-Mail: info@namlab.com


Cooperation:
cfaed – Center of Advancing Electronics Dresden (Germany)