Reconfigurable FETs On A Top-Down SOI Platform

A promising concept to leverage computing power beyond conventional Moore’s scaling is to extend the functional diversity of the basic electronic device, the transistor. NaMLab´s unique reconfigurable nanowire approach focuses on establishing a multifunctional electronics platform able to perform a higher number of functions with the same hardware complexity as conventional CMOS electronics. The reconfigurable nanowire field effect transistor (RFET) conceived at NaMLab and introduced already in 2008 is a four-terminal device that provides unipolar n- or p-type electrical characteristics at runtime as selected by an electric select signal (Fig. 1). Importantly, these devices are obtained without the need for doping and can by principle be fabricated with materials and processes established in volume silicon CMOS production facilities.

Fig. 1: Transfer characteristics of an RFET with selectable p-type (red) and n-type (blue) functionality built from a top-down SOI platform.

To enable the demonstration of more complex circuits and possible co-integration into modern CMOS flows the RFET technology was transferred from a bottom-up fabrication route to top-down process based on silicon on insulator (SOI) substrates. An omega shaped metal gate was used to increase the control over the nanowire channel. Thereby, stressor shells were successfully applied as enabler for symmetric drain-currents ensuring complementary operation of digital circuits. As an alternative method of barrier tuning, As dopant segregation after silicide contact formation has been studied. Different methods to control and reduce the variability in silicidation length of nanowires were established making the lab scale prototyping of simple demonstrator circuits possible. Appling those techniques, the RFET concept was extended to include a higher number of independent steering gates allocated along the channel (Fig. 2). The multi-independent-gate (MIG) approach efficiently bundles serial chains of FETs in a single device sparing interconnects and area for isolations, contacts and implantation wells. The MIG-RFET inherently provides a wired-AND function useful in many multi-input combinational circuits, such as majority gates or multiplexers.

Fig. 2: Top-view SEM image of a nanowire MIG-RFET built from a top-down SOI platform. Two individual control gates (CG) and two externally connected program gates (PG), source (S) and drain (D) are labeled. Scale bar is 2 µm.

In order to complement the work on horizontal RFETs, a feasibility study of RFETs based on vertically top-down nanowires was conducted by 3-D device simulations. Subdividing the RFET structure into two vertical pillars allows a lean technological realization as well as simple access to the electrodes (Fig. 3). We show that by the integration of additional vertical pillars and select gates, a higher device functionality and flexibility in interconnection are provided.

Fig. 3: Concept study of a vertical nanowire RFET integration on two pillars which are joined on an SOI body.

Contact

Dr. Jens Trommer
Senior Scientist
Phone: +49.351.21.24.990-00
E-Mail: info@namlab.com


Cooperation:
CfAED – Center of Advancing Electronics Dresden (Germany), DCN – Dresden Center for Nanoanalysis (Germany), Helmholtz Center Dresden Rossendorf (Germany)