Gallium Nitride Based Device Technology

The III-V compound semiconductor gallium nitride (GaN) has outstanding intrinsic material properties for power device applications. The NaMLab GaN device development is focused on electronic power devices with high voltage operation.  The High-Electron-Mobility-Transistor (HEMT) concept features  a 2‑dimensional electron gas (2DEG) at the AlxGayN/GaN heterojunction interface. It represents the backbone of GaN power transistors with planar or lateral current conduction close to the wafer surface. The material for industrial fabrication consists primarily of MOCVD grown GaN on Si(111) substrates with diameter of 150 mm or 200 mm.

A basic HEMT technology based on contact lithography for 150 mm wafer is utilized for material characterization in cooperation with external partners (Fig. 1). NaMLab is also working on process modules for improving overall device performance, stability and reliability. Related to the gate module, we investigate the integration of a high-k dielectric material underneath the gate electrode to fabricate a Metal-Insulator-Semiconductor (MIS)-HEMT. Compared to Schottky Gate HEMTs, MIS-HEMTs have the advantage of much lower gate leakage, but charge trapping effects at the dielectric/GaN interface have to be minimized for mature device operation. The second development is related to an alternative ohmic contact module based on Ta/Al metal bilayers compared to the mainstream Ti/Al contacts. Material engineering resulted in Ta/Al/TiN-ohmic contacts with low resistivity at much lower annealing temperatures (≤ 600°C), which are gold-free and enable a higher integration flexibility.

Fig. 1: Cross section MIS-HEMT device, process modules under investigation marked with circles. Below: image of processed 150 mm GaN-on-Si HEMT wafer with zoom in test chip die.

Another device development path is related to vertical GaN power devices, having the advantage of an almost area-independent scaling of the breakdown voltage. NaMLab is developing vertical GaN MOSFET devices with trench gate configuration and device channel along the vertical sidewall of the trench (Fig. 2). The device processing technology was first implemented on pseudo-vertical devices due to better material availability. Device functionality with threshold voltage in an appropriate range (VTH > 3 V) could be demonstrated and process improvement reduced charge trapping at the gate channel interface and increased the carrier mobility and current drive (Fig. 3). For increasing high voltage blocking capability (> 600 V), the technology is currently transferred from pseudo- to true vertical technology with backside contact on 2-inch free‑standing GaN substrates with larger drift layer thickness. Besides further module development, the focus on device level shifts from single trench cell test devices to power demo-devices with multiple gate trenches connected in parallel.


Dr. Andre Wachowiak

Dr. Andre Wachowiak
Senior Scientist
Phone: +49 351 2124990-00

Freiberger Compound Materials GmbH, Freiberg (Germany), TU Dresden (IHM) (Germany), TU-BA Freiberg (Germany),  RWTH Aachen (Germany), X-FAB (Germany)