The increasing amount of data being processed in today’s electronic devices for classification tasks in image and audio recognition, autonomous driving, smart sensors signal processing or machine learning, requires a transition from the conventional compute centric paradigm to a more data centric paradigm. In the classical von Neumann architecture, the data is transferred between computing and memory units via a bus system with limited bandwidth, giving rise to the well-known von Neumann bottleneck. In order to bridge the existing gap between memory and logic units, the concept of physical separation between computing and memory unit has to be repealed.
FeFET devices co-integrated into CMOS can be adopted as localized storage element in digital logic circuits. One example is image processing, where e.g. images are fed as a serial data stream through a digital filter. Coefficients of the filter kernel are stored as digital values directly inside the logic circuit, as is depicted in Fig. 1. In this example, three FeFET devices are used as local digital memory elements in a dynamic full-adder circuit.
While the digital computation has the benefit of a large signal-to-noise ratio, in analog computing circuits the data is represented by multiple intermediate states of a physical parameter such as threshold voltage of transistors or resistance of ferroelectric tunneling junctions (FTJ) and corresponding readout currents. These concepts benefit from the increase of information density per memory device, thus increasing the computation performance while lowering the power consumption per operation. Fig. 2 depicts an example by a logic-in-memory (LiM) operation. Multiple ferroelectric tunneling junctions (FTJ) that memorize digital data as different polarization states are read out in parallel. By evaluating the resulting sum current and comparing it to a threshold value Ith, different logic operations are realized.
Brain inspired and neuromorphic computing emulates the vast parallelism of the biological archetype to boost the system performance. An extremely low power consumption is attained by adopting the concepts of synergized memory and computing functionality within one single device, an increase of information density by utilizing analogue switching mechanisms in densely connected convolutional neural networks, and the adoption of time dependent information processing where the temporal correlation between the signals contains additional information. The team investigates the adoption of FeFETs to realize artificial neuron circuits by making use of the accumulative ferroelectric switching effect. Fig. 3 depicts the measured integrate-and-fire functionality of a single FeFET device upon cumulative excitation with programming pulses of different amplitudes.
Dr. Stefan Slesazeck
GLOBALFOUNDRIES (Germany/USA), École Centrale de Lyon (France), University Bielefeld (Germany)