Electrical measurements are essential for the characterization of the materials that are used to create electronic devices and circuits. NaMLab adopts a broad spectrum of electrical measurement techniques and analysis methods for device characterization. This includes capacitance measurements, such as C(V), C(T) and C(f), current measurements with down to femtoampere resolution at temperatures between 5 K and 450 K and voltages up to 3000 V. Samples can be analyzed by direct probing on wafer level using single probes, probe cards or special RF-probes. Package level testing can be performed for long-term reliability characterization or for the adoption of our devices in test-circuits. In addition, carrier lifetime measurements are available on substrates with microwave-detected photoconductivity.
The established methods at NaMLab include:
- Analysis of single memory cells (memory window, retention, endurance, …) by static and pulsed measurements
- Determination of transistor and capacitor characteristic curves by C-V and I-V measurements
- Determination of sheet resistance for thin layers.
- Determination of doping profiles by scanning spreading resistance Microscopy (SSRM)
- Reliability characterization of dielectric and transistors
- Defect characterization by charge pumping and charge trapping, analysis and defect spectroscopy
- Measurement of charge carrier mobility with Hall and split-C(V)
- Pulsed and high frequency measurements
- Power device characterization
Electrical material characterization such as the four point probe measurement is regularly used to attain fast feedback loops, thus supporting the material development (Fig. 1).
Besides the utilization of standard single device measurements, customized characterization setups are created at NaMLab. This work includes the development of special circuits that are mandatory to control non-standard test environments. Fig. 2 shows such an adaptive level-shifter circuit used for the digital control of a memory test array. The investigation of a novel memory device concept required the adaption of the operation voltage of the complete memory chip including the I/O voltages in order to optimize the operation conditions of the novel devices under test.
In Fig. 3 the measured bit-map of one quarter of a 64kBit memory array is shown. This measurement was performed in order to characterize the top-metallization layer which was manufactured at NaMLab on top of a 28 nm CMOS test chip.
Dr. Stefan Slesazeck